As the critical dimensions on CMOS integrated circuits scale down, series resistance is becoming an increasingly important limitation for transistor performance. Series resistance mainly arises from the following three sources in the transistor: the lightly doped drain (LDD) structure, the contact and line resistance, and the channel resistance. The LDD structure which is necessary to reduce hot electron degradation is the largest contributor to the total series resistance in the transistor. The effect of series resistance on transistor drive current (Ion) is a function of the current itself and the higher conductivity of NMOS transistors make them more susceptible to series resistance effects than PMOS transistors.
Currently, the LDD structure is formed using sidewall spacers and self aligned ion implantation. Typically, after the gate structure is formed, a self aligned implant is performed to form the LDD structures in regions adjacent to the transistor gate. N-type dopant species are implanted in NMOS transistors and p-type dopant species are implanted in PMOS transistors. Following this LDD implant, a thick layer of silicon nitride is formed and anisotropically etched to form sidewall structures adjacent to the gate of both the NMOS and PMOS transistors. Source and drain implants are then performed to form the heavily doped source and drain regions for both transistor types. During the annealing of the implanted species, diffusion will cause the LDD region to shift under the gate regions. This diffusion will be larger for the PMOS transistors due to the use of boron in the LDD and source and drain regions.
A reduction in the series resistance of the transistor can be achieved by reducing the sidewall thickness thereby shortening the LDD regions. This shortening will however result in the overrun of the LDD regions in the PMOS transistors caused by diffusion from the source drain regions. This will lead to increased transistor leakage currents rendering the circuit inoperable. There is a therefore a need for a method of tuning the sidewall spacers for both the NMOS and PMOS transistors without adding cost and complexity to the process.